For combinational logic, ensure every signal read in the process is in the sensitivity list. For sequential logic (flip-flops), only include the clock and the asynchronous reset.
Use assert and report statements to automate the verification process rather than relying on manual waveform inspection. effective coding with vhdl principles and best practice pdf
In VHDL-2008, you can use process(all) to automatically include all necessary signals, reducing the risk of latches. Avoid Unintentional Latches For combinational logic, ensure every signal read in
ieee.std_logic_1164.all and ieee.numeric_std.all . Process Blocks and Sensitivity Lists For combinational logic
Since VHDL projects often live for decades, maintainability is crucial.